- VLEN：向量寄存器宽度：单个向量寄存器的bits（固定）
- ELEN：元素宽度：单个向量元素的最大bits（VLEN≥ELEN）。它必须大于或等于 8，是 2 的幂次。
- SEW：选定的元素宽度：选定元素宽度，表示向量寄存器中当前选定元素的宽度。它充当分频器，将向量寄存器分解为该指定宽度的多个元素。
- LMUL：向量寄存器组乘法器：向量寄存器组乘法器，允许将多个向量寄存器打包到一个组中。LMUL 的值可以是 1/8、1/4、1/2、1、2、4 或 8，从而可以灵活地配置向量运算。
- VL：矢量长度：向量长度表示特定指令将操作的元素数量。VL 必须小于或等于 VLMAX，以确保有效的矢量运算。
- VLMAX：最大可操作元素数量：最大向量长度，是基于当前 SEW 和 LMUL 设置，使用单个矢量指令可以操作的最大元素数。它定义了向量运算的上限。
VLMAX = LMUL * VLEN / SEW - VSTART：起始元素：指定操作在向量寄存器中的开始位置。
VLEN 通常在 CPU 设计期间确定，而 SEW 和 LMUL 可以使用软件指令进行配置，从而为不同的应用提供灵活性。一旦设置了SEW和LMUL，VLMAX就建立起来了，为后续的矢量指令定义了最大的可操作元素。但是，矢量指令可以对较少的元素进行操作，如通过VL寄存器指定的那样。
- EEW：有效元素宽度
- EMUL：effective LMUL
- AVL：应用向量长度, 也就是要处理的数据的向量长度
大多数指令的大多数操作数，EEW=SEW 且 EMUL=LMUL，某些向量指令的源向量操作数和目标向量操作数的元素数量相同但宽度不同，因此 EEW 和 EMUL 分别不同于 SEW 和 LMUL，但 EEW/EMUL = SEW/LMUL
RISCV-V CSR
| Address | Privilege | Name | Description |
| 0x008 | URW | vstart | 向量起始位置 |
| 0x009 | URW | vxsat | 固定点饱和标志 |
| 0x00A | URW | vxrm | 固定点舍入模式 |
| 0x00F | URW | vcsr | 矢量控制和状态寄存器 |
| 0xC20 | URO | vl | 向量长度 |
| 0xC21 | URO | vtype | 向量数据类型寄存器 |
| 0xC22 | URO | vlenb | VLEN/8（向量寄存器长度（以字节为单位）） |
vtype
| Bits | Name | Description |
| XLEN-1 | vill | 如果设置则为非法值 |
| XLEN-2:8 | 0 | 如果非零则保留 |
| 7 | vma | 向量掩码不可知 |
| 6 | vta | 向量尾部不可知 |
| 5:3 | vsew[2:0] | 选定元素宽度 (SEW) 设置 |
| 2:0 | vlmul[2:0] | 向量寄存器组乘数 (LMUL) 设置 |
vsew 中的值设置动态选定元素宽度 (SEW)。默认情况下，向量寄存器被视为被划分为 VLEN/SEW 个元素。
LMUL 由 vtype 中的带符号 vlmul 字段设置（即 LMUL = 2^vlmul[2:0]）。 推导出的值 VL(MAX) = LMUL*VLEN/SEW 表示在给定当前 SEW 和 LMUL 设置的情况下，单个向量指令可以操作的最大元素数量
vl 寄存器保存一个无符号整数，用于指定要使用向量指令结果更新的元素数量
VLEN=32，LMUL=8 且 SEW=8，则 VL(MAX)=32
vset{i}vl{i}
vsetvli rd, rs1, vtypei # rd = new vl, rs1 = AVL, vtypei = new vtype setting
vsetivli rd, uimm, vtypei # rd = new vl, uimm = AVL, vtypei = new vtype setting
vsetvl rd, rs1, rs2 # rd = new vl, rs1 = AVL, rs2 = new vtype value汇编语法向 vset{i}vl{i} 指令添加了两个强制标志：
ta # Tail agnostic
tu # Tail undisturbed
ma # Mask agnostic
mu # Mask undisturbed
vsetvli t0, a0, e32, m4, ta, ma # Tail agnostic, mask agnostic
vsetvli t0, a0, e32, m4, tu, ma # Tail undisturbed, mask agnostic
vsetvli t0, a0, e32, m4, ta, mu # Tail agnostic, mask undisturbed
vsetvli t0, a0, e32, m4, tu, mu # Tail undisturbed, mask undisturbed
Suggested assembler names used for vset{i}vli vtypei immediate
e8 # SEW=8b
e16 # SEW=16b
e32 # SEW=32b
e64 # SEW=64b
mf8 # LMUL=1/8
mf4 # LMUL=1/4
mf2 # LMUL=1/2
m1 # LMUL=1, assumed if m setting absent
m2 # LMUL=2
m4 # LMUL=4
m8 # LMUL=8
Examples:
vsetvli t0, a0, e8, ta, ma # SEW= 8, LMUL=1
vsetvli t0, a0, e8, m2, ta, ma # SEW= 8, LMUL=2
vsetvli t0, a0, e32, mf2, ta, ma # SEW=32, LMUL=1/2vsetvl 变体的操作与 vsetvli 类似，只是它从 rs2 获取 vtype 值并且可用于上下文恢复。
Vector Unit-Stride Instructions
# Vector unit-stride loads and stores
# vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>)
vle8.v vd, (rs1), vm # 8-bit unit-stride load
vle16.v vd, (rs1), vm # 16-bit unit-stride load
vle32.v vd, (rs1), vm # 32-bit unit-stride load
vle64.v vd, (rs1), vm # 64-bit unit-stride load
# vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>)
vse8.v vs3, (rs1), vm # 8-bit unit-stride store
vse16.v vs3, (rs1), vm # 16-bit unit-stride store
vse32.v vs3, (rs1), vm # 32-bit unit-stride store
vse64.v vs3, (rs1), vm # 64-bit unit-stride store# Vector unit-stride mask load
vlm.v vd, (rs1) # Load byte vector of length ceil(vl/8)
# Vector unit-stride mask store
vsm.v vs3, (rs1) # Store byte vector of length ceil(vl/8)
Vector Strided Instructions
# Vector strided loads and stores
# vd destination, rs1 base address, rs2 byte stride
vlse8.v vd, (rs1), rs2, vm # 8-bit strided load
vlse16.v vd, (rs1), rs2, vm # 16-bit strided load
vlse32.v vd, (rs1), rs2, vm # 32-bit strided load
vlse64.v vd, (rs1), rs2, vm # 64-bit strided load
# vs3 store data, rs1 base address, rs2 byte stride
vsse8.v vs3, (rs1), rs2, vm # 8-bit strided store
vsse16.v vs3, (rs1), rs2, vm # 16-bit strided store
vsse32.v vs3, (rs1), rs2, vm # 32-bit strided store
vsse64.v vs3, (rs1), rs2, vm # 64-bit strided store
Vector Indexed Instructions
# Vector indexed loads and stores
# Vector indexed-unordered load instructions
# vd destination, rs1 base address, vs2 byte offsets
vluxei8.v vd, (rs1), vs2, vm # unordered 8-bit indexed load of SEW data
vluxei16.v vd, (rs1), vs2, vm # unordered 16-bit indexed load of SEW data
vluxei32.v vd, (rs1), vs2, vm # unordered 32-bit indexed load of SEW data
vluxei64.v vd, (rs1), vs2, vm # unordered 64-bit indexed load of SEW data
# Vector indexed-ordered load instructions
# vd destination, rs1 base address, vs2 byte offsets
vloxei8.v vd, (rs1), vs2, vm # ordered 8-bit indexed load of SEW data
vloxei16.v vd, (rs1), vs2, vm # ordered 16-bit indexed load of SEW data
vloxei32.v vd, (rs1), vs2, vm # ordered 32-bit indexed load of SEW data
vloxei64.v vd, (rs1), vs2, vm # ordered 64-bit indexed load of SEW data
# Vector indexed-unordered store instructions
# vs3 store data, rs1 base address, vs2 byte offsets
vsuxei8.v vs3, (rs1), vs2, vm # unordered 8-bit indexed store of SEW data
vsuxei16.v vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data
vsuxei32.v vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data
vsuxei64.v vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data
# Vector indexed-ordered store instructions
# vs3 store data, rs1 base address, vs2 byte offsets
vsoxei8.v vs3, (rs1), vs2, vm # ordered 8-bit indexed store of SEW data
vsoxei16.v vs3, (rs1), vs2, vm # ordered 16-bit indexed store of SEW data
vsoxei32.v vs3, (rs1), vs2, vm # ordered 32-bit indexed store of SEW data
vsoxei64.v vs3, (rs1), vs2, vm # ordered 64-bit indexed store of SEW data
Unit-stride Fault-Only-First Loads
# Vector unit-stride fault-only-first loads
# vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>)
vle8ff.v vd, (rs1), vm # 8-bit unit-stride fault-only-first load
vle16ff.v vd, (rs1), vm # 16-bit unit-stride fault-only-first load
vle32ff.v vd, (rs1), vm # 32-bit unit-stride fault-only-first load
vle64ff.v vd, (rs1), vm # 64-bit unit-stride fault-only-first load
Vector Load/Store Segment Instructions
Vector Unit-Stride Segment Loads and Stores
# Format
vlseg<nf>e<eew>.v vd, (rs1), vm # Unit-stride segment load template
vsseg<nf>e<eew>.v vs3, (rs1), vm # Unit-stride segment store template
# Examples
vlseg8e8.v vd, (rs1), vm # Load eight vector registers with eight byte fields.
vsseg3e32.v vs3, (rs1), vm # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to mem
# Example 1
# Memory structure holds packed RGB pixels (24-bit data structure, 8bpp)
vsetvli a1, t0, e8, ta, ma
vlseg3e8.v v8, (a0), vm
# v8 holds the red pixels
# v9 holds the green pixels
# v10 holds the blue pixels
# Example 2
# Memory structure holds complex values, 32b for real and 32b for imaginary
vsetvli a1, t0, e32, ta, ma
vlseg2e32.v v8, (a0), vm
# v8 holds real
# v9 holds imaginary
# Template for vector fault-only-first unit-stride segment loads.
vlseg<nf>e<eew>ff.v vd, (rs1), vm # Unit-stride fault-only-first segment loads
Vector Strided Segment Loads and Stores
# Format
vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm # Strided segment loads
vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm # Strided segment stores
# Examples
vsetvli a1, t0, e8, ta, ma
vlsseg3e8.v v4, (x5), x6 # Load bytes at addresses x5+i*x6 into v4[i],
# and bytes at addresses x5+i*x6+1 into v5[i],
# and bytes at addresses x5+i*x6+2 into v6[i].
# Examples
vsetvli a1, t0, e32, ta, ma
vssseg2e32.v v2, (x5), x6 # Store words from v2[i] to address x5+i*x6
# and words from v3[i] to address x5+i*x6+4
Vector Indexed Segment Loads and Stores
# Format
vluxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-unordered segment loads
vloxseg<nf>ei<eew>.v vd, (rs1), vs2, vm # Indexed-ordered segment loads
vsuxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-unordered segment stores
vsoxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm # Indexed-ordered segment stores
# Examples
vsetvli a1, t0, e8, ta, ma
vluxseg3ei32.v v4, (x5), v3 # Load bytes at addresses x5+v3[i] into v4[i],
# and bytes at addresses x5+v3[i]+1 into v5[i],
# and bytes at addresses x5+v3[i]+2 into v6[i].
# Examples
vsetvli a1, t0, e32, ta, ma
vsuxseg2ei32.v v2, (x5), v5 # Store words from v2[i] to address x5+v5[i]
# and words from v3[i] to address x5+v5[i]+4
Vector Load/Store Whole Register Instructions
# Format of whole register load and store instructions.
vl1r.v v3, (a0) # Pseudoinstruction equal to vl1re8.v
vl1re8.v v3, (a0) # Load v3 with VLEN/8 bytes held at address in a0
vl1re16.v v3, (a0) # Load v3 with VLEN/16 halfwords held at address in a0
vl1re32.v v3, (a0) # Load v3 with VLEN/32 words held at address in a0
vl1re64.v v3, (a0) # Load v3 with VLEN/64 doublewords held at address in a0
vl2r.v v2, (a0) # Pseudoinstruction equal to vl2re8.v v2, (a0)
vl2re8.v v2, (a0) # Load v2-v3 with 2*VLEN/8 bytes from address in a0
vl2re16.v v2, (a0) # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0
vl2re32.v v2, (a0) # Load v2-v3 with 2*VLEN/32 words held at address in a0
vl2re64.v v2, (a0) # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0
vl4r.v v4, (a0) # Pseudoinstruction equal to vl4re8.v
vl4re8.v v4, (a0) # Load v4-v7 with 4*VLEN/8 bytes from address in a0
vl4re16.v v4, (a0)
vl4re32.v v4, (a0)
vl4re64.v v4, (a0)
vl8r.v v8, (a0) # Pseudoinstruction equal to vl8re8.v
vl8re8.v v8, (a0) # Load v8-v15 with 8*VLEN/8 bytes from address in a0
vl8re16.v v8, (a0)
vl8re32.v v8, (a0)
vl8re64.v v8, (a0)
vs1r.v v3, (a1) # Store v3 to address in a1
vs2r.v v2, (a1) # Store v2-v3 to address in a1
vs4r.v v4, (a1) # Store v4-v7 to address in a1
vs8r.v v8, (a1) # Store v8-v15 to address in a1csrr t0, vl # Save current vl (potentially not needed)
vsetvli t1, x0, e8, m8 # Maximum VLMAX
vlm.v v0, (a0) # Load mask register
vsetvli x0, t0, <new type> # Restore vl (potentially already present)
如果rs1 != 0 (x0), 也就是AVL(应用向量长度)=rs1, 此时进行正常的stripmining. 设置rd的值为vl
如果rs1 == 0,
①. 如果rd == 0 (x0), 保持vl为上次计算的vl
②. 如果rd != 0 (x0), 设置vl = VLMAX, 设置rd的值为vl
向量掩码
用于控制屏蔽向量指令执行的屏蔽值始终由向量寄存器 v0 提供。
| vm | Description |
| 0 | v0.mask[i]=1 |
| 1 | unmasked |
向量掩码在汇编代码中表示为另一个向量操作数，其中 .t 表示当 v0.mask[i] 为 1 时发生该操作（t 表示“true”）。如果未指定屏蔽操作数，则假定未屏蔽向量执行 (vm=1)。
vop.v* v1, v2, v3, v0.t # enabled where v0.mask[i]=1, vm=0
vop.v* v1, v2, v3 # unmasked vector operation, vm=1
addressing modes
- unit-stride
- strided
- indexed (scatter/gather)
| mop[1:0] | Description | Opcodes |
|---|---|---|
| 0 0 | unit-stride | VSE<EEW> |
| 0 1 | indexed-unordered | VSUXEI<EEW> |
| 1 0 | strided | VSSE<EEW> |
| 1 1 | indexed-ordered | VSOXEI<EEW> |
向量unit-stride 和constant-stride内存访问不保证各个元素访问之间的顺序。向量 indexed-ordered加载和存储内存操作有两种形式：有序和无序。索引排序变体保留内存访问的元素顺序。
对于无序指令 (mop[1:0]!=11)，不保证元素访问顺序。如果访问是针对强有序 IO 区域，则可以按任何顺序启动元素访问。
Implementation-defined Constant Parameters
Vector Extension Programmer’s Model
Mapping of Vector Elements to Vector Register State
Vector Instruction Formats
Configuration-Setting Instructions (vsetvli/vsetivli/vsetvl)
Vector Loads and Stores
Vector Memory Alignment Constraints
Vector Memory Consistency Model
Vector Arithmetic Instruction Formats
Vector Integer Arithmetic Instructions
Vector Fixed-Point Arithmetic Instructions
Vector Floating-Point Instructions
Vector Reduction Operations
Vector Mask Instructions
Vector Permutation Instructions
Exception Handling
Standard Vector Extensions
Vector Instruction Listing
vadd vredsum vfadd
vredand vfredusum
vsub vredor vfsub
vrsub vredxor vfredosum
vminu vredminu vfmin
vmin vredmin vfredmin
vmaxu vredmaxu vfmax
vmax vredmax vfredmax
vaaddu vfsgnj
vand vaadd vfsgnjn
vor vasubu vfsgnjx
vxor vasub
vrgather
vslideup vslide1up vfslide1up
vrgatherei16
vslidedown vslide1down vfslide1down
vadc VWXUNARY0 VWFUNARY0
VRXUNARY0 VRFUNARY0
vmadc
vsbc VXUNARY0 VFUNARY0
vmsbc VFUNARY1
VMUNARY0
vmerge/vmv vcompress vfmerge/vfmv
vmseq vmandnot vmfeq
vmsne vmand vmfle
vmsltu vmor
vmslt vmxor vmflt
vmsleu vmornot vmfne
vmsle vmnand vmfgt
vmsgtu vmnor
vmsgt vmxnor vmfge
vsaddu vdivu vfdiv
vsadd vdiv vfrdiv
vssubu vremu
vssub vrem
vmulhu vfmul
vsll vmul
vmulhsu
vsmul vmulh vfrsub
I vmv<nr>r
vsrl vfmadd
vsra vmadd vfnmadd
vssrl vfmsub
vssra vnmsub vfnmsub
vnsrl vfmacc
vnsra vmacc vfnmacc
vnclipu vfmsac
vnclip vnmsac vfnmsac
vwredsumu vwaddu vfwadd
vwredsum vwadd vfwredusum
vwsubu vfwsub
vwsub vfwredosum
vwaddu.w vfwadd.w
vwadd.w
vwsubu.w vfwsub.w
vwsub.w
vwmulu vfwmul
vwmulsu
vwmul
vwmaccu vfwmacc
vwmacc vfwnmacc
vwmaccus vfwmsac
vwmaccsu vfwnmsac
vmv.s.x
vmv.x.s
vpopc
vfirst
vzext.vf8
vsext.vf8
vzext.vf4
vsext.vf4
vzext.vf2
vsext.vf2
vfmv.s.f
vfmv.f.s
vfcvt.xu.f.v
vfcvt.x.f.v
vfcvt.f.xu.v
vfcvt.f.x.v
vfcvt.rtz.xu.f.v
vfcvt.rtz.x.f.v
vfwcvt.xu.f.v
vfwcvt.x.f.v
vfwcvt.f.xu.v
vfwcvt.f.x.v
vfwcvt.f.f.v
vfwcvt.rtz.xu.f.v
vfwcvt.rtz.x.f.v
vfncvt.xu.f.w
vfncvt.x.f.w
vfncvt.f.xu.w
vfncvt.f.x.w
vfncvt.f.f.w
vfncvt.rod.f.f.w
vfncvt.rtz.xu.f.w
vfncvt.rtz.x.f.w
vfsqrt.v
vfrsqrt7.v
vfrec7.v
vfclass.v
vmsbf
vmsof
vmsif
viota
vid
Reserved Writes Preserve Values, Reads Ignore Values (WPRI)
Write/Read Only Legal Values (WLRL)
Write Any Values, Reads Legal Values (WARL)
Machine-Level CSRs
Machine ISA Register
misa CSR（WARL）存储支持的指令集和扩展信息
Machine Vendor ID Register
mvendorid CSR 存储处理器供应商的唯一标识符
Machine Architecture ID Register
marchid CSR 存储处理器架构的唯一标识符
Machine Implementation ID Register
mimpid CSR 存储处理器实现的唯一标识符
Hart ID Register
mhartid CSR 存储处理器的硬件线程 ID，用于多处理器系统
Machine Status Registers
mstatus and mstatush CSR 机器模式状态寄存器，存储处理器的当前运行状态和特权级别
Machine Trap-Vector Base-Address Register
mtvec register 机器模式陷阱向量基地址寄存器，存储异常处理程序的入口地址
Machine Trap Delegation Registers
medeleg and mideleg 机器模式陷阱委托寄存器，用于委托异常处理到更低特权级别
Machine Interrupt Registers
mip and mie 机器模式中断挂起寄存器和中断使能寄存器，用于管理中断
Hardware Performance Monitor
mcycle CSR and minstret CSR 硬件性能监视器，用于计数 CPU 周期和指令执行次数
Machine Counter-Enable Register
mcounteren 机器模式计数器使能寄存器，用于控制特定计数器的使能
Machine Counter-Inhibit CSR
mcountinhibit 机器模式计数器抑制寄存器，用于抑制计数器的计数
Machine Scratch Register
mscratch 机器模式暂存寄存器，用于保存临时数据
Machine Exception Program Counter
mepc 机器模式异常程序计数器，用于存储发生异常时的程序计数器的值
Machine Cause Register
mcause 机器模式异常原因寄存器，存储导致异常的原因代码
Machine Trap Value Register
mtval 机器模式异常附加值寄存器，存储与异常相关的附加信息
Machine Configuration Pointer Register
mconfigptr 机器模式配置指针寄存器，用于配置硬件环境
Machine Environment Configuration Registers
menvcfg and menvcfgh 机器模式环境配置寄存器，用于配置硬件环境
Machine Security Configuration Register
mseccfg 机器模式安全配置寄存器，用于配置硬件的安全设置
Machine-Level Memory-Mapped Registers
Machine Timer Registers
mtime and mtimecmp
Machine-Mode Privileged Instructions
Environment Call and Breakpoint
ECALL
EBREAK
Trap-Return Instructions
MRET/SRET
Wait for Interrupt
WFI
Custom SYSTEM Instructions
Supervisor CSRs
Supervisor Status Register
sstatus
Supervisor Trap Vector Base Address Register
stvec
Supervisor Interrupt Registers
sip and sie
Supervisor Timers and Performance Counters
time, cycle, and instret CSRs
Counter-Enable Register
scounteren
Supervisor Scratch Register
sscratch
Supervisor Exception Program Counter
sepc
Supervisor Cause Register
scause
Supervisor Trap Value Register
stval
Supervisor Environment Configuration Register
senvcfg
Supervisor Address Translation and Protection Register
satp
Supervisor Instructions
SFENCE.VMA